1. Field of Invention
This invention relates in general to a method of manufacturing semiconductor components having a titanium nitride (TiN) layer, and more particularly to a method of manufacturing a semiconductor component suitable for application in shallow junction and self-aligned suicide processes which can lower the formation temperature of C-54 phase titanium silicide (C-54 TiSi.sub.2), and hence increase the stability of components.
2. Description of Related Art
Conventional self-aligned silicide processes are commonly applied to the fabrication of very large scale integration (VLSI) products that have a linewidth of less than about 0.5 m. When the level of integration for semiconductor components is increased, resistance in the source or drain region of a metal-oxide-semiconductor (MOS) component will correspondingly increase until it is comparable with the resistance of the MOS channel. In order to lower the sheet resistance of the source and drain terminals, as well as ensuring the integrity of the shallow junction between a metal layer and the MOS, self-aligned silicide processes or salicide processes are employed.
FIGS. 1A through 1D are a series of cross-sectional views showing the manufacturing steps of a salicide process. First, referring to FIG. 1A, an MOS transistor having a gate 11, source/drain regions 12, and spacers 13 are formed above a silicon substrate 10. A metallic layer 14 with a thickness of about 200 .ANG. to 1000 .ANG. is then deposited on the surface of the silicon substrate 10 through a magnetron DC sputtering method as shown in FIG. 1B. Subsequently, upon application of a high temperature, part of the metallic layer 14 reacts with silicon above the source/drain regions 12 and polysilicon above the gate 11 of the MOS transistor, thereby forming silicide layers 15, as shown in FIG. 1C. The unreacted residual metal remaining after the reactive process is then removed by a wet etching method, thereby leaving behind the metal silicide layers 15 on the top surfaces of the MOS terminals, as shown in FIG. 1D.
Titanium (Ti) is one of the most commonly used materials for the salicide processes. Other materials utilized include cobalt (Co), nickel (Ni), and platinum (Pt). The metal suicide layer formed by a conventional salicide process, such as a titanium silicide layer, has two basic structures, a metastable C-49 phase titanium silicide (C-49 TiSi.sub.2) structure, and a thermodynamically more stable C-54 phase titanium silicide (C-54 TiSi.sub.2) structure having a lower resistance. C-49 phase titanium silicide has a resistance of between about 60 .mu..OMEGA./cm to 90 .mu..OMEGA./cm and a formation temperature of between about 400.degree. C. to 500.degree. C. C-54 phase titanium silicide has a lower resistance of between about 14 .mu..OMEGA./cm to 16 .mu..OMEGA./cm, but a rather high formation temperature of between about 700.degree. C. to 750.degree. C. In the manufacturing process, generally the higher resistance C-49 phase titanium silicide will be transformed to a lower resistance C-54 phase titanium silicide through the application of a rapid thermal processing (RTP). However, when a VLSI techniques is used for the production of integrated circuits having linewidths of less than about 0.25 m, the formation temperature of C-54 phase titanium silicide will rise to between about 800.degree. C. and 900.degree. C. due to the linewidth size effects. This so-called linewidth size effect is the relationship between the linewidth and the phase transformation temperature. According to this relationship, as the linewidth gets smaller, the transformation temperature necessary for the change from the higher resistance C-49 phase to the lower resistance C-54 phase increases. If the temperature used in RTP is raised to within the formation temperature of a C-54 phase titanium silicide, the titanium silicide layer so formed will have rather unstable properties and may therefore be unsuitable for small dimensional devices. Hence, how to lower the formation temperature for C-54 phase titanium silicide in small dimensional devices has become a major research topic for both academic institutions as well as semiconductor manufacturers.
Conventional methods for lowering the formation temperature of C-54 phase titanium silicide include the interposition of a heat resisting refractory metallic layer such as a molybdenum (Mo) or tungsten (W), or the use of an ion doped amorphous semiconductor substrate formed below the required metal silicide layer. However, the above methods, while still being in the experimental state, will all increase the complexity of the manufacturing process. Therefore, as to date, such methods cannot be directly applied to the fabrication of wafers.